Conventional bipolar integrated circuit logic circuits operate at low voltage logic levels. Typically, a low or zero logic level as specified for TTL logic circuits may range from 0.0 to 0.8 volt. A high or one level may be specified by any voltage in the range of 2 volts to 5 volts. Thus, in order to distinguish between logic "0" levels and logic "1" levels, a circuit must be capable of switching between a "0" level and a "1" level somewhere between 0.8 and 2 volts, preferably at approximately 1.4 volts in order to give the widest margins of reliability.
While TTL logic operates at the voltage and switching levels noted above, with a supply voltage V.sub.CC typically being 5 volts, MOS logic, and particularly CMOS logic may operate at higher voltages, with a supply voltage V.sub.DD typically being in a range of 4.5 to 15 volts. Since the high available densities of MOS circuitry make MOS technology particularly suitable for very large scale integrated circuits or functions, and since much of the interface circuitry used to provide inputs and controls to the VLSI MOS functions are TTL level circuits, a convenient mechanism must be available to translate TTL logic levels to MOS levels such that, on the remainder of the MOS monolithic circuit, gates of the MOS FETs can be driven between ground and V.sub.DD.
One very desirable attribute of a level shifting circuit is the maintanence of an accurate and well defined switch point, above which the TTL to MOS level shifting circuit will recognize an input as a "1" logic level and below which it will recongize a "0" logic level input, and translate these to 5 or 0 volts at the output of the circuit, respectively.
High-speed level shifters are conventionally implemented with low gain differential comparators. While such circuits are fast, they are also quite large and draw significant amounts of current. Additionally, such circuits require bias lines which usually have associated therewith external resistors.
The instant invention provides a circuit which, while not as fast as these noted above, is small, draws very little power, and requires no external resistors or biasing lines.
Other prior art circuits utilized an input inverter stage with a P-channel transistor having its drain connected to the drain of an N-channel transistor and the gates connected together to form an input node. The source of the P-channel transistor was connected to V.sub.DD (the positive voltage supply) and the source of the N-channel transistor was connected to V.sub.SS (the lowest or negative voltage supply). When v.sub.DD was 5 volts and V.sub.SS was 0 volts, it was possible to select the transistor size ratios such that the switch point of the inverter approximated 1.4 volts.
As long as the supply (V.sub.DD) at which the chip was to operate did not vary significantly, the switch point of the previously mentioned level shifter could be reasonably closely controlled by selecting the ratios of the transistors of the input inverter in such a manner as to provide the proper switch point.
As the difference in voltage between the source of the P-channel device and the source of the N-channel device increased, i.e., as V.sub.DD increased with respect to V.sub.SS, the ratio between the N-channel and P-channel device strengths had to increase to maintain the switch point of the level shifter. The P-channel device was made weaker than the N-channel device because the P-channel device has a higher gate to source voltage than the gate to source voltage of the N-channel device at the switch point. A high ratio of N-channel to P-channel device strength creates problems in MOS IC layout, because the P-channel device typically has a small width and large channel length. As can be shown from the simulatneous application of the saturated current equations and the transconductance equations for both the P-channel and N-channel devices, a low N to P strength ratio is also desirable since the level shifter switch point can be controlled better over process and operating conditions. Therefore, the inclusion of a bipolar transistor (connected as a transistor or a diode) between the source of the P-channel device and V.sub.DD provides a P-source to N-source voltage of V.sub.DD -V.sub.BE volts. When V.sub.DD is 5 volts, the P-channel source voltage is approximately 4.4 volts, allowing a smaller ratio between the N-channel and P-channel device strengths because the gate to source voltage of the P-channel device is smaller at the switch point.
If it is desired to operate the chip at a voltage V.sub.DD in excess of 5 volts (or with a range of voltage V.sub.DD) it becomes difficult to maintain the switchpoint within specified limits. Accordingly, an object of this invention is to provide a level shift circuit which allows operation with V.sub.DD at various levels while maintaining a desired input switch point.